省電模式與喚醒1,前言

圖1,Deep Sleep Mode

目前業界對於MCU 普遍有 1高2低的需求.
一高 指的是 高效能,二低 指的是低單價以及低功耗.

• 高效能,相較於8051,LPC1100 系列的 Core : Arm Cortex-M0 標榜著 Dhrystone 0.9 DMIPS/MHz (印象中數據,最快的8051 宣稱能達到 0.1 DMIPS),加上32 bit 運算,最高CPU Clock 可達到50MHz. 在MCU的Core可算是高效能的MCU之一.
• 低價位, 在NXP的資料中,LPC1111FHN/101 起價於0.65美金.當然8051有0.4美金以下的更低價位,不過對比於ARM7時期的32Bit MCU價位來說,目前的Cortex-M0的價格已經低很多,且大大壓縮8Bit MCU的價位.(國內新唐還宣稱至 0.55美金起.....)
• 低功耗,  Arm Cortex-M0 標榜著 85 µW/MHz ,因為 Cortex-M0 core只要 12K gates (與8051相近). 而NXP在增加了周邊線路後 09' 年 150uA/MHz ,10' 年 130uA/MHz, 11'年會推出 100uA/MHz. 在省電模式下也有不同方式達成低功耗.

去年的某案子中就量測過省電模式下的耗電狀況(圖1).
那時候還是自己試了很久才寫出來的.不過現在官網上已經放上AN,完整的省電模式範例都到位.而且還是基於LPCXpresso所做的(去年是用Keil MDK開發). 對於目前為止以LPCXpresso 作為DIY 平台的 MCU DIY來說,一定也要來利用這篇AN一下.(最近好像都追隨AN Release 真是偷懶 !! XD)


廢話不多說先去下載 AN11027
AN11027 Using the LPC1100 low power modes and wake-up times on the LPCXpresso
裡面有 文件說明以及兩部分Sample code.LPC1100 wakeup.zip & LPC1100 self wakeup.zip,

實驗中會學習到幾個主題(AN11027中所提的5點):

1. 瞭解LPC111x省電模式
2. 進入省電模式的方式
3. 省電模式喚醒實作
4. 降低耗電的提示
5. 如何使用LPCXpresso Board操作省電模式

所以就來談談省電模式
LPC111x中的省電模式(Low Power)分為: Sleep, Deep-sleep mode, Deep power-down mode.
由下表1可見以上幾種模式下耗電數據:

表1

表上半部為第一代的數據,下半部為目前第二代數據

資料中對幾個模式的說明如下:


2.1.1   Sleep mode
In Sleep mode, the system clock to the ARM Cortex-M0 core is stopped, and execution
of instructions is suspended until either a reset or an enabled interrupt occurs. 
Peripheral functions, if selected to be clocked in the SYSAHBCLKCTRL register,
continue operation during Sleep mode and may generate interrupts to cause the
processor to resume execution. Sleep mode eliminates dynamic power used by the
processor itself, memory systems and their related controllers, and internal buses. The
processor state and registers, peripheral registers, and internal SRAM values are
maintained, and the logic levels of the pins remain static.
2.1.2   Deep-sleep mode
In Deep-sleep mode, the system clock to the processor is disabled as in Sleep mode. All
analog blocks are powered down, except for the BOD circuit and the watchdog oscillator,
which must be selected or deselected during Deep-sleep mode in the PDSLEEPCFG
register. See section 3.5 for more details.
Deep-sleep mode eliminates all power used by the flash, analog peripherals and all
dynamic power used by the processor itself, memory systems and their related
controllers, and internal buses. The processor state and registers, peripheral registers,
and internal SRAM values are maintained, and the logic levels of the pins remain static.
2.1.3   Deep power-down mode
In Deep Power-down mode, power and clocks are shut off to the entire chip with the
exception of the  WAKEUP  pin.
During Deep power-down mode, the contents of the SRAM and registers are not retained
except for a small amount of data which can be stored in five 32-bit general purpose
registers of the power management unit block. 
All functional pins are tri-stated in Deep power-down mode except for the  WAKEUP  
pin.

很多字又很小(怕看倌認真讀上面的三段文字),不過這邊稍微整理列表後,簡單看出差異,各省電模式下差異
更省電就是代表關掉更多區塊.
更省電就是代表能維持狀況的區塊更少.
更省電就是代表,喚醒後到程式執行的所需時間越長.

下一篇:
省電模式與喚醒2-1,LPC1100 wakeup